1. Field of the Invention
The present invention relates to reticles (photo masks), a semiconductor device manufactured by using the reticles, and a method of manufacturing the same.
2. Description of the Related Art
FIG. 1 is a schematic perspective view illustrating a process of transferring a pattern of a reticle (photo mask) to a semiconductor chip. Tens of reticles 50, each carrying a particular pattern 62 having a size N times, e.g., 5 times, larger than that of the pattern formed on the chip 2, are prepared in advance according to each of required patterns for a semiconductor device. The pattern 62 of the reticle 50 is sequentially transferred to the chips 2 by means of an optical 1/N reduction projection technique. Defect-free reticles 50 are needed since the defects of the reticles 50 are transferred to all the semiconductor chips 2 if the reticles 50 have defects. It is required that each reticle be aligned with high precision to prevent a misalignment of the mask since tens of reticles have to be used. A resist layer is coated on the wafer 1. The resist is molten only in those areas where it is irradiated by the light to produce a pattern. After the processes are completed, the chips 2 are cut on the scribe lines 3. Reference numeral 55 in FIG. 1 denotes a reduction optical system.
FIG. 2 is an enlarged plan view of a reticle. Usually, a reticle 50 comprises a transparent glass substrate 61 and a pattern-forming film 62 made of a metal such as chromium. The glass substrate 61 has on its surface the pattern-forming film 62 used for forming semiconductor elements and a reticle inspection mark (QC mark) 64 used for ensuring the dimensional accuracy of the mask and determining the quality of the reticle. The inspection mark 64 is located in a scribe line-forming area 63 on the surface of the glass substrate 61, which corresponds to the scribe line 3 of a wafer 1. A vernier 65 used for achieving an accurate alignment of the reticle 50 is provided in the scribe line-forming area 63. Reference numeral 66 in FIG. 1 denotes the chip-forming area of the reticle 50.
FIG. 3 is a plan view of a conventional wafer 1. A plurality of semiconductor chips 2 are formed on the wafer 1. First, second and third marks 4, 5, and 6 are formed at given locations on scribe lines 3 separating the chips 2, by using first, second and third reticles. In other words, the marks 4, 5, and 6 are produced there by transferring the inspection marks 64 each formed on the first, second and third reticles. A large number of QC (quality control) marks, such as dimensional reference marks and aligning marks, need to be formed on the scribe lines 3. Since the first, second and third marks 4, 5, and 6 must be required to occupy a minimum surface area, they are formed on the same area, overlapping one another.
FIG. 4 is a sectional view of the wafer 1 taken along a I--I line in FIG. 3. A silicon substrate 7 has a first insulation film 8 formed on its surface. A first silicide wiring layer 9 is deposited on the first insulation film 8. The layer 9 is in an amorphous state. The layer 9 is subjected to patterning by means of a lithography technique using the first reticle, thereby forming a first mark 4. Then, the first silicide wiring layer 9, which is still in an amorphous state, is annealed, turning into a polycrystalline state which has a reduced resistance. Simultaneously, the first mark 4 is also rendered polycrystalline. Next, a second insulation film 11 is formed on the first mark 4 and the first insulation film 8. Then, the second mark 5, that is, an opening 12 which is located on the first mark 4, is formed in the second insulation film 11 by the lithography technique using the second reticle. The sides of the opening 12 are aligned with the sides of the first mark 4. Thereafter, a second silicide wiring layer 13 is deposited on the second insulation film 11, filling the opening 12. The layer 13 is subjected to patterning by means of the lithography technique using the third reticle whereby the third mark 6 is formed in and on the opening 12. The sides of the third mark 6 are aligned with the sides of the opening 12. In other words, if the first mark 4 (first silicide wiring layer 9), the second mark 5 (opening 12), and the third mark 6 (second silicide wiring layer 13) are aligned with one another, the patterns produced by the reticles will be aligned accurately on the silicon substrate 7.
As described above, the first silicide wiring layer 9 is formed on the semiconductor chip 2 by the lithography technique using the first reticle, and the second insulation film 11 is deposited on the first silicide wiring layer 9. Then, a contact hole (not shown) is formed in the second insulation film 11 by means of the lithography technique using the second reticle. The size of the contact hole includes an alignment margin to allow for a possible misalignment of the reticles. The second silicide wiring layer 13 is deposited on the second insulation film 11 and in the contact hole and then is formed as the second silicide wiring by the lithography technique using the third reticle. The second silicide wiring is also large enough to allow for a possible misalignment of the third reticle.
FIGS. 5 and 6 are respectively a plan view and a sectional view illustrating the misalignment of the marks 4, 5 and 6 caused by the misalignment of the reticles. As shown in FIG. 5, if the third reticle is misaligned within the alignment margin, the third mark 6 which is formed on the scribe line 3 between the adjacent chips 2 is displaced with respect to the first and second marks 4 and 5. If the third mark 6 is so displaced, a part 9a of the first silicide wiring layer 9, already in a polycrystalline state, will be over-etched, as illustrated in FIG. 6, when the second silicide wiring layer 13 is etched using the third reticle. Since the polycrystalline silicide wiring layer 9 is etched at different rates inside the grain and on the grain boundary and depending on the face orientation of the grain, grains may be scraped and separated from the silicide wiring layer 9 as the etching proceeds along the grain boundaries. The grains, thus scraped, make dust which reduces the yield of semiconductor chips, i.e., LSIs.
FIG. 7 is a sectional view illustrating a vernier 49 formed on a scribe line 3 of a conventional wafer 1. The vernier 49 is formed by transferring the vernier 65 formed on a scribe line-forming area 63 of the reticle 50 on the wafer 1. The principal calibration 4a of the vernier 49 is formed in a pattern at the same time when the first silicide wiring layer 9, i.e., the first mark 4 is formed. The auxiliary calibration (the opening) 5a of the vernier 49 is formed in another pattern simultaneously when the opening 12 is formed for the second mark 5. The vernier 49, thus formed, can serve to determine the precision of alignment of the patterns transferred on the wafer 1. However, some of the grains of the silicide serving as the principal calibration 4a of the vernier 49 may also be scraped during the etching process using the third reticle, thus producing dust which will reduce the yield of LSIs.